XR79110EL-F

The XR79110EL-F is a non-isolated Point-of-Load (PoL) module from MaxLinear that delivers up to 10A from a 4.5V to 22V input, with an adjustable output from 0.6V to 5.5V and a peak efficiency of 96%. When a prototype returns from the lab with a hot module after five minutes of operation, or an EMC pre-compliance scan fails after swapping vendors, the root cause is rarely the silicon itself. The following four failure modes account for over 80% of field issues with this part in the DC DC Converters category. Each section follows the sequence: symptom, probable causes, diagnostic steps, and corrective action.

Failure 1: Module Runs Hot Above 85°C Junction After Five Minutes at 8A

Symptom: The XR79110EL-F case reaches 85°C–100°C within five minutes at 8A output, even with 200 LFM airflow. Efficiency drops to below 88%.

Probable causes: Insufficient PCB copper area beneath the 72-PowerBFQFN module, missing thermal via array, or incorrect output capacitor ESR (effective series resistance). The 4.0mm tall module relies on the system board for heat extraction; the bottom-side exposed pad must be soldered to a minimum of two inner-layer copper pours.

Diagnostic steps:

• Measure the board temperature 2mm from the module edge with a thermocouple. The difference between module case and board copper should not exceed 15°C at steady state.
• Check that the output capacitor bank has a total ESR below 50 mΩ at 100 kHz. A high-ESR cap increases ripple current in the inductor, which raises core losses.
• Verify that the bottom layer under the module has at least four thermal via holes (0.3mm diameter, filled with solder) connecting the pad to a ground plane.

Fix: Redesign the landing pattern to include a 10×10mm copper pad on the top layer with at least six vias connecting to a solid inner-layer ground plane. Reduce output capacitor ESR by using ceramic X7R or low-ESR polymer types. Consult the latest XR79110EL-F datasheet for the recommended layout copper area based on ambient temperature.

Failure 2: Conducted Emissions Spike at 150 kHz After Module Swap

Symptom: An existing design passed EN 55032 Class B with a previous PoL module. After replacing it with the XR79110EL-F, conducted emissions exceed the limit by 8 dB at 150 kHz.

Probable causes: Switching frequency shift due to different internal oscillator tolerance, or input ripple coupling onto the power bus. The XR79110EL-F operates with a nominal switching frequency; if the upstream input filter resonates near this frequency, ripple current amplifies.

Diagnostic steps:

• Measure the switching frequency at the switch node (test point on inductor pin) with a 10x probe. Compare against the datasheet range.
• Examine input voltage ripple at the module input pins using a 100 MHz bandwidth scope. Ripple amplitude above 100 mVpp indicates input filter mismatch.
• Calculate the resonant frequency of the input LC filter (L_input and total input capacitance). If it falls between 100 kHz and 200 kHz, it will amplify the fundamental switching harmonic.

Fix: Increase input capacitance to shift the LC resonance below 20 kHz or damp it with a 1Ω series resistor in the filter. If the switch frequency is within spec, add a 1 nF ceramic capacitor directly across the module input pins to bypass high-frequency transients. For the XR79110EL-F cross-reference, ensure the input filter inductor is rated for the full 10A DC current without saturation.

Failure 3: Output Fails to Ramp Up During Power-On Sequencing

Symptom: The output stays below 0.3V when the enable pin is pulled high, or the module latches off and requires a power cycle to restart.

Probable causes: Violation of the power-up sequence requirement — the XR79110EL-F needs its input voltage to reach the UVLO threshold (typically 4.5V) before the enable pin is asserted. Applying enable before input causes the internal soft-start circuit to see an undervoltage lockout event, latching the module off. Alternatively, the pre-bias on the output (a voltage already present from another rail) can confuse the start-up state machine.

Diagnostic steps:

• Using a two-channel scope, monitor input voltage ramp and enable pin voltage simultaneously. Verify that input voltage reaches 4.5V at least 5 ms before enable crosses 1.2V.
• Check the output for any residual voltage prior to start-up (pre-bias from a parallel LDO or bulk capacitor discharge). Pre-bias above 0.5V may cause the module to enter overcurrent protection during soft-start.
• Measure the soft-start capacitor value if one is used externally (pin 19, if present in the design). An open capacitor causes fast ramp-up with high inrush current.

Fix: Add an RC delay on the enable pin to ensure a minimum 10 ms delay after input rail is stable. If pre-bias exists, use a module with pre-bias start-up capability or discharge the output before enable. For this product family, typical values range from 0.1 μF to 1 μF for the soft-start capacitor; ensure the correct value per the XR79110EL-F input voltage specifications.

Failure 4: Output Voltage Droops 120 mV During FPGA Core Load Transient

Symptom: When the FPGA toggles from idle to full compute load, the output of the XR79110EL-F droops by 120 mV, causing logic errors in the downstream device.

Probable causes: The output capacitor bank has insufficient capacitance or the control loop bandwidth is limited by a high-ESR output capacitor. The 10A PoL module has a typical transient response; the output voltage deviation during a 5A step change is a function of the output capacitance and the ESR of the capacitors.

Diagnostic steps:

• Capture the transient waveform at the output capacitor terminals using a 20 MHz bandwidth setting on the scope. Measure the droop magnitude and recovery time (should be < 50 μs for this power level).
• Calculate the total output capacitance: for a 5A load step with a 50 mV allowable droop, the minimum required capacitance is (5A × 50 μs) / 50 mV = 5000 μF, assuming the control loop bandwidth of 20 kHz. Adjust for actual bandwidth.
• Check the capacitor voltage rating: a 6.3V rated cap on a 5.5V output fails derating — derating reduces effective capacitance by 30%–50% for X5R dielectrics.

Fix: Replace the output capacitor with low-ESR ( 5 mΩ) ceramic capacitors mounted as close as possible to the module output pins. Increase total output capacitance to at least 4× the datasheet recommended value for high-speed loads. If the transient occurs above 1 MHz, add 10 μF × 2 of 0805-size capacitors with X7R dielectric. For precise values, refer to the XR79110EL-F pinout to identify which output pins require the lowest inductance routing.

The two most critical specs for application design are the output current derating curve (not shown in the table but implied by the operating temperature range) and the input voltage UVLO threshold. A common oversight is assuming the module delivers 10A at 22V input without regard for ambient temperature; at 105°C ambient, the current must be derated by approximately 20% to stay below the 125°C junction limit. The UVLO hysteresis (typically 200 mV) means that once the input drops below 4.3V, the module shuts off and does not restart until the input rises back above 4.5V — a problem in systems with slow-ramping supplies or brownout conditions. Always add margin to the input rail to avoid cycle-by-cycle power-on reset.

Five-Step Preventive Design Checklist for XR79110EL-F

Before committing the layout to fabrication, verify these five items:

1. Thermal vias: Place a 6×6 array of 0.3mm vias under the exposed pad, connecting to a ground plane on layer 2. Ensure the vias are filled with non-conductive epoxy or solder mask to prevent solder wicking.
2. Input capacitance: Use at least 10 μF of ceramic capacitance plus a 100 μF electrolytic capacitor within 10mm of the input pins. Place a 0.1 μF high-frequency bypass capacitor directly at the input pin.
3. Output ripple budget: For output voltages below 1.2V, total output capacitance should be minimum 200 μF with ESR under 10 mΩ to keep ripple below 1% of Vout.
4. Enable sequencing: If the input voltage ramp is slower than 1V/ms, add a RC network (10 kΩ, 1 μF) between input and enable pin to delay enable assertion by at least 5 ms after input reaches 4.5V.
5. Transient check: Simulate a 5A load step with a 1A/μs slew rate. If droop exceeds 3% of Vout, increase output capacitance by 50% or add a bulk capacitor with low ESL.